1. Field of the Invention
This invention is related to the field of processors and, more particularly, to operand sizes in processors.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
The x86 architecture specifies a variable length instruction set (i.e. the size of the various instructions in the instruction set may differ). By providing variable length instructions, each instruction occupies only the amount of memory needed to specify that instruction and any operands thereof. For example, the x86 architecture specifies an instruction set having instructions anywhere from one byte in length to 15 bytes. Thus, the amount of memory occupied by a code sequence may be optimized, as compared to fixed length instruction sets which tend to occupy more memory. In other words, the code density (number of instructions/unit memory) may be higher for variable length instruction sets than for fixed length instruction sets for a given code sequence. Not only is the efficient use of memory possible, but delays in fetching the instructions from memory may be, on average, lower since a given set of bytes fetched from memory may include more variable byte length instructions than fixed length instructions.
As computer systems have continued to evolve, 64 bit address size (and sometimes operand size) has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64 bit address and/or operand sizes. Thus, it may be desirable to provide an architecture which is compatible with the x86 processor architecture but which includes support for 64 bit processing as well.
Providing an x86 compatible processor architecture which supports 64 bit processing may exacerbate the problem of operand size selection. In the x86 architecture, the active operating mode specifies a default operand size for instructions and prefix bytes are used for instructions in which a different operand size is desired. If such a mechanism were extended to 64 bit modes, the additional available operand size may lead to additional use of prefix bytes to select the non-default operand size when desired. Since the prefix bytes increase the size of the instruction, code density may decrease. A mechanism for efficient operand size selection is therefore desired.
A processor is described which supports a mode in which the default operand size is 32 bits, but which supports operand size overrides to 64 bits. Furthermore, the default operand size may automatically be overridden to 64 bits for instructions having an implicit stack pointer reference and for near branch instructions. The overriding of the default operand size may occur without requiring an operand size override encoding in these instructions. For these instructions, it may frequently be more desirable to have the 64 bit operand size, while it may more frequently be desirable to have the 32 bit operand size for many other instructions. In one embodiment, the instruction set specifying the instructions may be a variable byte length instruction set (e.g. x86), and the operand size override encoding may be a prefix byte which increases the instruction length. For such embodiments, code density may be improved for code sequences which generally use a 32 bit operand size but would use a 64 bit operand size for the instructions having an implicit stack reference and near branch instructions.
Broadly speaking, a processor is contemplated. The processor comprises a circuit configured to generate an indication of a default operand size, and an execution core coupled to receive a first instruction. The execution core is configured to override the default operand size with a second operand size responsive to the first instruction having an implicit stack pointer reference.
Additionally, a method is contemplated. A default operand size is generated for instructions. The default operand size is overridden with a second operand size for a first instruction responsive to the first instruction having an implicit stack pointer reference.
Moreover, a processor is contemplated. The processor comprises a circuit configured to generate an indication of a default operand size. Coupled to receive a near branch instruction, the execution core is configured to override the default operand size with a second operand size responsive to the near branch instruction.
Still further, a method is contemplated. A default operand size is generated for instructions. The default operand size is overridden with a second operand size for a near branch instruction.